1. Field of the Invention
The present invention relates to a processing technique when a fault has occurred in a processor for executing a plurality of processes at a same time.
2. Description of the Related Art
A processor with a single CPU had been generally used for a control process. However, since the control process becomes higher in level and more complex, the single CPU has become impossible to execute the whole of process. For this reason, a multi-processor system is developed where a plurality of CPUs execute a plurality of processes at a same time. Here, it is supposed that the multi-processor system executes a process A of a process A1 and a process A2. Also, it is supposed that the multi-processor system has a CPU 1 and a CPU 2 and they execute the process A1 and the process A2, respectively. In this case, if the CPU 1 and the CPU 2 can normally execute the processes A1 and A2, the process A is completed without any problem. However, in such a multi-processor system, if one of the plurality of CPUs is inoperable, the entire system is down. For example, when the CPU 1 is in a frozen state or in a fault state in which an indefinite loop is executed, the process A1 to be executed by the CPU 1 is not completed. For this reason, even if the CPU 2 can normally complete the process A2, the process A is not completed. Also, since the process A is not completed, the CPU 2 cannot start a next process even if completing the process A2. In this way, the entire multi-processor processor cannot be normally operated.
The technique related to a multi-processor system is disclosed in Japanese Laid Open Patent Publication (JP-P2000-76199A). In this conventional example, a CPU issues a request signal to an arbitrator circuit. The arbitrator circuit executes a bus arbitration and gives a bus use right (grant signal) to the CPU. When the bus is released, the CPU issues a completion signal to the arbitrator circuit. Then, the bus is released in accordance therewith. In this way, the switching between the CPUs (the control of the occupation/relief of input/output I/F) is executed by reserving the bus use right.